The present invention relates to a semiconductor integrated circuit device including a macro cell on which three or more wiring layers is required to be formed, and its manufacturing method. Particularly, the present invention relates to a semiconductor integrated circuit device in which a plurality of macro cells whose originally necessary number of metal wiring layers differs is embedded on the same semiconductor chip, and its manufacturing method.
Moreover, the present invention relates to a large scale integrated circuit (LSI) in which an ASIC (application-specific integrated circuit) section and a semiconductor memory section are embedded, and its manufacturing method.
In recent years, in the manufacture of LSI, there is a case in which a plurality of kinds of macro cells is embedded on the same semiconductor chip. In this case, the originally necessary number of metal wiring layers, which is formed on a semiconductor substrate, differs.
For example, as shown in FIG. 1, there is a case in which an ASIC section 61 and a memory section 62 are formed in an adjacent area on an LSI chip 60. Further, as shown in FIG. 2, there is a case in which an ASIC section 61 having three wiring layers and a memory section having two wiring layers are embedded on a semiconductor substrate 70.
On the LSI chip 60, ASIC section 60 has a first wiring layer 71, a second wiring layer 72, and a third wiring layer 73. Though the memory section 62 has the first and second wiring layers, but no third wiring layer 73.
In FIG. 2, reference numeral 72a shows a first contact plug for connecting the second wiring layer 72 to the first wiring layer 71. Reference numeral 73a shows a second contact plug for connecting the third wiring layer 73 to the second wiring layer 72. Reference numeral 74 is a first insulating layer on the semiconductor substrate. Reference numeral 75 is a second insulating layer on the first wiring layer 71. Reference numeral 76 is a third insulating layer on the second wiring layer 72. Reference numeral 77 is a fourth insulating layer formed on the third wiring layer 76 of the memory section 62 and the third wiring layer 73 of the ASIC section 61.
In forming the third wiring layer 73 of the ASIC section 61 on the same chip as the memory section, a surface of the second wiring layer 72 is flattened in the conventional process as shown in FIG. 2. Due to this, a film thickness of the second wiring layer 72 is reduced, and its wiring resistance is increased. However, it is assumed that the macro cell whose number of the necessary wiring layers is small (memory cell section 62 in this example), the uppermost wiring layer (second wiring layer 72) is used as a power supply line. In this case, a potential drop, which is caused by an increase in the wiring resistance, is increased. Also, it is assumed that the uppermost wiring layer is used as a signal line, which determines an operation velocity of the memory, that is, a critical path. In this case, a wiring delay is increased by an increase in the wiring resistance. Due to this, an electrical characteristic (performance) as an LSI chip is lowered.
Thus, in the conventional LSI in which a plurality of macro cells whose originally necessary number of metal wiring layers differs is embedded on the same semiconductor chip, the film thickness of the wiring layer having a macro cell whose number of the necessary wiring layers is small is reduced, and its wiring resistance is increased. As a result, the potential drop and the wiring delay are increased by the increase in the wiring resistance.
An object of the present invention is to provide a semiconductor integrated circuit device, which can restrict an increase in wiring resistance and prevent an increase in a potential drop and a wiring delay caused by the wiring resistance when a plurality of macro cells whose originally necessary number of metal wiring layers differs is embedded on the same chip, and its manufacturing method.
According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device comprising: a semiconductor substrate having first and second macro cells each having a plurality of elements formed; and wiring layers of N layers (Nxe2x89xa73) formed on said semiconductor substrate sequentially from a first wiring layer to an N-th wiring layer, wherein Nxe2x88x921 wiring layer on said first macro cell includes a first wiring pattern having a plurality of pattern segments, N-th wiring layer on said first macro cell includes a second wiring pattern having one or more same pattern segments among the plurality of pattern segments, and the plurality of pattern segments include one or more contact pattern, respectively.
According to a second aspect of the present invention, there is provided a semiconductor integrated circuit device comprising: a semiconductor substrate having first and second macro cells each having a plurality of elements formed; and wiring layers of N layers (Nxe2x89xa73) formed on said semiconductor substrate sequentially from a first wiring layer to an N-th wiring layer, wherein Nxe2x88x922 wiring layer on said first macro cell includes a first wiring pattern having a plurality of pattern segments, each of said plurality of pattern segments has at least one contact pattern, Nxe2x88x921 wiring layer on said first macro cell includes one or more same contact pattern as the contact pattern formed on said first wiring pattern, and the Nth wiring layer on said first macro cell includes a second wiring pattern having one or more same pattern segments among the plurality of pattern segments.
According to a third aspect of the present invention, there is provided a semiconductor integrated circuit device comprising: a semiconductor substrate having a plurality of macro cells whose necessary number of metal wiring layers differs; and a plurality of metal wiring layers formed on said semiconductor substrate, wherein an uppermost wiring layer of the macro cell whose necessary number of metal wiring layers is smaller is formed of the same wiring layer as an uppermost wiring layer of the macro cell whose necessary number of metal wiring layers is larger.
According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit device in which first and second macro cell regions whose necessary number of metal wiring layers formed on a semiconductor substrate differs are embedded on the same chip comprising the step of: forming an uppermost wiring layer of the macro cell whose necessary number of metal wiring layers is smaller is formed of the same wiring layer as an uppermost wiring layer of the macro cell whose necessary number of metal wiring layers is larger.
According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit device comprising the steps of: forming a semiconductor substrate having first and second macro cells each having a plurality of elements formed; and forming wiring layers of N layers (Nxe2x89xa73) on said semiconductor substrate sequentially from a first wiring layer to an N-th wiring layer, the step of forming the wiring layers of N layers includes a sub-step of forming said Nxe2x88x921 wiring layer to include a first pattern having a plurality of pattern segments, and a sub-step of forming said N-th wiring layer on said first macro cell to include a second wiring pattern having one or more same pattern segments among the plurality of pattern segments, and the plurality of pattern segments include one or more contact pattern, respectively.
According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit device comprising the steps of: forming a semiconductor substrate having first and second macro cells each having a plurality of elements formed; and wiring layers of N layers (Nxe2x89xa73) formed on said semiconductor substrate sequentially from a first wiring layer to an N-th wiring layer, wherein the step of forming said wiring layers of N layers includes: a sub-step of forming said Nxe2x88x922 wiring layer such that the Nxe2x88x922 wiring layer on said first macro cell includes a first wiring pattern having a plurality of pattern segments wherein each of said plurality of pattern segments has at least one contact pattern: a sub-step of forming said Nxe2x88x921 wiring layer such that said Nxe2x88x921 wiring layer on said first macro cell includes one or more same contact pattern as the contact pattern formed on said first wiring pattern; and a sub-step of forming said Nth wiring layer such that said Nth wiring layer on said first macro cell includes a second wiring pattern having one or more same pattern segments among the plurality of pattern segments.
Thus, according to the above-mentioned structure and the method, the increase in the wiring resistance can be restricted even if the film thicknesses of the wiring layer of the macro cell whose originally necessary number of wiring layers is small is reduced when a plurality of macro cells whose originally necessary number of metal wiring layers is embedded on the same semiconductor chip. As a result, the potential drop caused by the increase in the wiring resistance and the increase in the wiring delay can be restricted, thereby preventing the deterioration of the performance.
Additional object and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The object and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.